The present invention relates to a semiconductor memory device; more particularly, to a semiconductor memory device capable of inactivating an on-die termination circuit without an additional pin.
A variety of semiconductor devices embodied by an integrated circuit chip, such as a CPU, a memory and a gate array, have been combined in electrical products such as a personal computer, a server and an work station. Most of the semiconductor devices include an input circuit for receiving external signals through an input pad and an output circuit for outputting internal signals through an output pad.
As an operation speed of electrical products has increased, swing width of signals transmitted between semiconductor memory devices is required to decrease in order to minimize a delay time taken to transmit the signals. However, as the swing width of signals decreases, signal transmission is more affected by external noises and signal reflection in an interface terminal increases by impedance mismatching.
The impedance mismatching is caused by variation of a manufacture process, a supply voltage and an operation temperature (PVT). The impedance mismatching makes it hard to transmit data at a high speed. Because data outputted from a semiconductor device may be distorted by the impedance mismatching, malfunctions such as a set up/hold fail and misjudgment of data level could be caused in a corresponding semiconductor device receiving the distorted data.
Accordingly, a semiconductor device that a high operating speed is required of includes an impedance matching circuit, called on-die termination, near an I/O pad. Generally, a source termination is performed by an output circuit in a semiconductor device transmitting data. A parallel termination is performed by a termination circuit parallelly connected to an input circuit in a semiconductor device receiving data.
FIG. 1 is a block diagram illustrating an on-die termination circuit of a conventional semiconductor memory device. The on-die termination circuit includes a controlling unit 10 and an ODT output driver 20.
The controlling unit 10 controls a termination resistance by an external setting. The controlling unit 10 includes a control signal generator 12 and a buffer 14. The control signal generator 12 decodes an extend mode register set (EMRS) set externally and outputs control signals ODT_PU<1:3> and ODT_PD<1:3>. The buffer 14 buffers the control signals ODT_PU<1:3> and ODT_PD<1:3>. The buffer 14 compensates for decrease of the control signals ODT_PU<1:3> and ODT_PD<1:3> which are caused by noises when the control signal generator 12 is far from the ODT output driver 20. Accordingly the buffer 14 is unnecessary when the control signal generator 12 is close to the ODT driver 20.
The ODT driver 20 includes a plurality of output drivers 22, 24 and 26 turning on or off in response to the control signals ODT_PU<1:3> and ODT_PD<1:3>. Because output nodes of the output drivers 22, 24 and 26 are connected in common, each output driver is parallelly connected at the output node. As the number of the output drivers turning on by the control signals ODT_PU<1:3> and ODT_PD<1:3> increases, the number of resistors connected in parallel increases. Accordingly, the termination resistance decreases. On the other hand, as the number of the output drivers turning on decreases, the termination resistance increases. It is possible to control the termination resistance by setting the ERMS externally.
A method for estimating the termination resistance with respect to turn-on resistors of output drivers 22, 24 and 26 is described below. When each turn-on resistor of the output drivers has a resistance of 150 Ω and all output drivers are turned on, three turn-on resistors having the resistance of 150 Ω are connected in parallel. The termination resistance becomes 50 Ω. When two of output drivers are turned on, two of turn-on resistors are connected in parallel and the termination resistance becomes 75 Ω. When one of output drivers is turned on, the termination resistance becomes 150 Ω.
Accordingly, the termination resistance is able to be controlled by setting the EMRS externally. If required resistance is set into the EMRS, the control signal generator generates the control signals in order to turn on the output drivers according to the required resistance.
For example, when a resistance of 50 Ω is set into the EMRS, the control signal generator 14 enables all control signals ODT_PU<1:3> and ODT_PD<1:3> in order to turn on all output drivers 22, 24 and 26. When a resistance of 75 Ω is set into the EMRS, the control signal generator 14 enables corresponding control signals ODT_PU<1:2> and ODT_PD<1:2> in order to turn on two of output drivers 22, 24 and 26. When a resistance of 150 Ω is set into the EMRS, the control signal generator 14 enables corresponding control signals ODT_PU<1>and ODT_PD<1> in order to turn on one of output drivers 22, 24 and 26.
Meanwhile a semiconductor memory device with the above-mentioned on-die termination circuit can not receive commands or addresses from a part of test devices at multiple test operations. A plurality of test devices are connected to a semiconductor memory device in parallel and simultaneously perform test operations in order to perform the test operations fast. Because the plurality of test devices have different drivabilities from each other, commands or addresses from test devices having relatively less drivability can not be inputted into the semiconductor memory device due to decline of the drivability by the on-die termination circuit. On the other hand, test devices having relatively more drivability can perform test operations normally without decline of the drivability by the on-die termination circuit.
That is, each test device has its own output resistance and the termination resistance of the semiconductor memory device should be set to each output resistance. However, because the test devices are connected in parallel and operate simultaneously, the termination resistance of the semiconductor memory device is set to one resistance estimated in parallel. Accordingly, the test device having relatively less drivability among the plurality of test devices can not perform test operations normally.
In order to solve above mentioned problem, the conventional on-die termination circuit is turned off at the test operation. An additional pin through which a termination-off signal is inputted should be provided to turn off the on-die termination circuit at the test operation. When the termination-off signal is enabled, the control signal generator disables all control signals for the on-die termination circuit. The on-die termination circuit is turned off. However, it is difficult to provide the additional pin at the test operation.